VHDL Language and design flow
20-06-2016 :: imec Leuven, Belgium

Organizer: imec

This 5-day course VHDL language and design flow is centered on VHDL syntax (through example) while emphasizing good code style and the link to hardware. The increasing complexity of digital circuits brings the need for a design methodology that allows a short design cycle, while maintaining architectural flexibility, re-use of IP blocks and easy documentation. 

 
June 20-24
 
VHDL is a standard worldwide language for the design, documentation and description of electronic systems on the component, board or system level. It supports design verification through simulation and design creation through synthesis. 
 
Simulation and synthesis are however not the only tools used in the design flow of an ASIC. Digital frontend designers nowadays need also knowledge about a whole set of tools like e.g. static timing analysis, test insertion, power analysis and testpattern generation. 
 

During the course the participants will: 

 
  • Be introduced to VHDL and the test-bench concepts. 
  • Learn how to efficiently simulate VHDL models. 
  • Be introduced to the VHDL synthesizable sub-set. 
  • Learn that what you write is what you get, i.e. that the synthesized netlist is dependent on how the code is written. 
  • Learn how to tackle issues like: sharing, asynchronous logic, initialization. 
  • Get some experience with synthesis of the VHDL code into a gate level netlist using clock gating techniques to reduce the power. 
  • Learn how to insert basic test logic and generate testpatterns. 
  • Be introduced to performing power analysis, generating testpatterns and running logic equivalence checks. 

Who should attend

This course focuses on (junior) system design engineers targeting FPGA and ASIC.
 
More information
 










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