Advanced verification with UVM
23-01-2017 :: imec Leuven, Belgium

Organizer: imec

The 3-days UVM (Universal Verification Methodology) course is primarily targeted at IC design/verification engineers or managers who are looking for a real productivity gain for their functional verification problem.  The goal of this course is to raise the level of UVM awareness and knowledge to the point where users have sufficient confidence to adopt to this verification methodology.

 
The audience may benefit more if they are already aware of SystemVerilog, VHDL/Verilog, constrained random verification and object-oriented programming. The hands on labs shall comfort the audience to get more acquainted with the verification methodology.
 
This course will teach you on building tests and verification environments, reusing UVCs (Universal Verification Component) and stimulus, sequencers and sequences, help you to understand the use of factory and configuration database in customizing your verification.
 

Who should attend

 
The course is primarily targeted at IC design/verification engineers or managers who are looking for a real productivity gain for their functional verification problem.
 
This course will teach you on building tests and verification environments, reusing UVCs (Universal Verification Component) and stimulus, sequencers and sequences, help you to understand the use of factory and configuration database in customizing your verification. 
 
 
More information
 










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