Advanced Digital Physical Implementation flow
24-10-2017 :: imec

Organizer: imec

Are you interested in the changes introduced in the IC design flow for advanced deep-submicron technology nodes? Are you searching for a deeper understanding of the low-power issues? Do you want to know everything about relevant process parameters and IP-libraries? Or do you want to become familiar with future design flow challenges? A hands-on course with experts who daily face the dos-and-donts in physical design will bring you to the next level. State-of-the-art EDA tools and relevant design exercises in the 65-40nm technology bring you to a more advanced level of implementation skill.
State-of-the-art EDA tools and relevant design exercises will bring the participants to a level at which they can confidently face future design flow challenges introduced by the 65 nm process characteristics and constraints.

https://imec.csod.com/default.aspx?p=imec&c=Guest&dlink=%2fDeepLink%2fProcessRedirect.aspx%3fmodule%3dlodetails%26lo%3dc0b876f5-d77d-4a61-8991-c19f35ae2f1a











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